The use of current mode switching regulators to control a DC output voltage at a level higher than, lower than, or the same as an input voltage is well known. Typically, one or more switches are activated to supply current pulses via an inductor to charge an output capacitor. The output voltage level is maintained at a desired level by adjusting the on and off times of the switching pulses in accordance with output voltage and load conditions.
FIG. 1 is a block diagram of a typical current mode switching regulator. Switching control circuit 10 may comprise any of various known controllers that provide pulse width modulated output pulses to regulate a DC output voltage VOUT at a level that may be greater than, lower than, or the same as a nominal input voltage VIN. Typically, the control circuit includes a latch, having set and reset inputs, coupled to a controlled switch that supplies switched current ISW to inductor 12. Capacitor 14 is connected between the output VOUT and ground. Resistors 16 and 18 are connected in series between VOUT and ground. A load 20 is supplied from the regulator output.
The set input is coupled to clock 22, which may generate pulses in response to an oscillator. During normal operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator 24. An output voltage feedback signal VFB is taken at the junction of resistors 16 and 18 and coupled to negative input of error amplifier 26. A voltage reference VREF is applied to the positive input of error amplifier 26. Capacitor 28 is coupled between the output of error amplifier 26 and ground.
The level of charge of capacitor 28, and thus its voltage VC, is varied in dependence upon the output of amplifier 26. As load current increases, the output voltage, and thus VFB, decreases. As the feedback voltage VFB decreases, VC increases. Thus, VC is proportional to load current. VC is coupled to the inverting input of comparator 24. The non-inverting input is coupled to adder 30. Adder 30 combines signal ISW, which is proportional to the sensed switch current, with a compensation signal. Upon switch activation in response to a clock set signal, switch current builds through inductor 12. When the level of the signal received from adder 30 exceeds VC, comparator 24 generates a reset signal to terminate the switched current pulse. During heavier loads, VC increases and the switched current pulse accordingly increases in length to appropriately regulate the output voltage VOUT.
For normal regulator operation at duty cycles of fifty percent or higher, compensation is needed in the switching control to avoid sub-harmonic oscillation. A typical compensation approach is termed “slope compensation,” wherein a signal of increasing magnitude is added to the current signal ISW, or subtracted from the signal VC, during each switching cycle. FIG. 2 is a circuit diagram of a prior art slope compensation generator that may be input to adder 30 to modify the current signal applied to the non-inverting input of comparator 24. The output of the circuit is a current signal Sx, corresponding to the current in the series circuit path of transistor 32, resistor (R) 34 and voltage bias (VB) source 36. The base of transistor 32 is coupled to the output of unity gain buffer amplifier 38. The positive input of amplifier 38 is coupled to receive an oscillator generated ramp signal Vramp. The negative input of amplifier 38 is coupled to the junction between transistor 32 and resistor 34.
FIG. 3 is a simplified waveform diagram illustrative of the compensation function of the circuit of FIG. 2. The Vramp signal is a sawtooth format signal that is generated at the beginning of each clock cycle and extends at linear slope to the end of the cycle, corresponding to one hundred percent duty cycle. As an example, the Vramp magnitude may vary between zero and one volt. Transistor 32 begins conduction at a percent duty cycle point Ts at which Vramp overtakes the fixed voltage VB. As compensation is needed at fifty percent duty cycle operation or greater, VB typically is arbitrarily chosen at one half the value of the maximum Vramp level, or one half-volt in the present example. Ts thus will be at fifty percent duty cycle. As Vramp continues to increase after point Ts, the base signal applied to transistor 32 increases and, thus, the output current Sx increases linearly to a maximum Smax at the end of the switching cycle. Sx is determined by (Vramp-VB)/R. The compensation curve Sx starting point Ts is thus determined by VB, and its slope is determined by R. In this example, Ts occurs at fifty percent of the switching cycle at the oscillator operating frequency, regardless of the actual switch duty cycle. Compensation is provided throughout an operational range of fifty to one hundred percent switch duty cycle.
FIG. 4 is a circuit diagram of a typical oscillator circuit used for producing the Vramp signal. Constant current source 102 is connected in series with capacitor 104. Coupled across capacitor 104 is the series arrangement of controlled switch 106, shown schematically, and constant current source 108. Switch 106 assumes a closed, or conductive, state in response to a high logic level output of comparator 110. The positive input of comparator 110 is coupled to the junction between constant current source 102 and capacitor 104. The negative input of comparator 110 is coupled to the series arrangement of resistor 112 and voltage reference threshold source 114. Transistor 116 is coupled in parallel with resistor 112 and source 114.
With switch 106 in the open state as shown, charge is applied to capacitor 104 to build up its voltage at a constant rate until it exceeds the voltage at the negative input, Vn, of the comparator 110. At that point, the comparator outputs a signal to activate the switch 106 to a conductive state, thereby coupling the capacitor to constant current source 108 to discharge capacitor 104. As the current source 108 is much greater than the current source 102, and the comparator is configured with sufficient hysteresis, the capacitor is quickly discharged to its base minimum level voltage. The voltage at capacitor 104 produces the Vramp signal. In the absence of application of an activation signal to the base of transistor 116, the circuit operates as a free running oscillator. The charge and discharge cycle is repeated continuously at a constant frequency dependent upon the time necessary for the voltage at capacitor 104 to rise from its base level to its threshold level of reference source 114. The time required for capacitor discharge is negligible.
The oscillator may be controlled to operate at a higher frequency by application of a higher frequency synchronous signal to the base of transistor 116. When a synchronizing pulse is applied to the base of transistor 116, the negative input to comparator 110 is coupled to ground, causing the immediate closure of switch 106 and discharge of capacitor 104 by current discharge source 108. Upon discharge of the capacitor to the base voltage level of Vramp, the comparator ceases its output signal, switch 106 again transitions to an open state, and charge is again applied to capacitor 104 to build the Vramp signal. The circuit thus will provide a Vramp signal output at the higher frequency with decreased charging period for capacitor 104.
The waveforms of FIGS. 5A-5D illustrate operation in both the free running and synchronized oscillator modes. Waveform (a) represents an external voltage signal, Vsync, applied to the base of transistor 116. Waveform (b) represents the voltage at the negative input to comparator 110. Waveform (c) represents the Vramp signal. The Vramp signal is applied to the positive input of amplifier 38 of FIG. 2. Waveform (d) represents the compensation signal Vcomp. For comparison with the waveform of FIG. 3, it is assumed that the voltage threshold source 114 is one volt and that the base line level is zero volt. 100 kHz is taken as an example of the free running oscillator frequency.
Between time t0 and t2, Vsync (waveform a) is zero, whereby the circuit operates as a free running oscillator at 100 kHz. Vramp (waveform c) exhibits a constant slope from a value of 0.0 volt at t0 to the threshold 1.0 volt at t1. The slope is dependent on the value of capacitor 104 and constant current charge source 102. Vn (waveform b) drops to 0.0 volt level from 1.0 volt during the brief period of transition of Vramp from its maximum to minimum levels. The compensation signal, Vcomp, is initiated when the Vramp signal attains the voltage VB of the reference source 32. This point is at fifty percent duty cycle, as described above with respect to FIGS. 2 and 3.
Waveforms (a)-(d) repeat as described until time t2, when a Vsync signal having a frequency of 150 kHz is applied to the base of transistor 116. At that time, the voltage Vn at the negative input to comparator 110 is forced low, the Vramp signal attains the 0.0 volt level and then begins to increase. As there has been no change to the constant current charge source 102 or to the capacitor 104, the slope of Vramp remains the same. At time t3, the next Vsync pulse occurs, again forcing Vn low to terminate the Vramp pulse. As the Vsync frequency of 150 kHz is greater than the 100 kHz frequency at free running operation, the time during which charge can build on capacitor 104, i.e., between t2 and t3, has decreased. The maximum value of the Vramp signal is 0.66 volt.
The effect of application of the 150 kHz Vramp signal to the positive input of amplifier 38 on compensation signal Vcomp is as follows. As the voltage bias (VB) source 36 remains at 0.5 volt and the slope of Vramp remains the same, the length of time required to initiate the compensation signal in each cycle remains the same. The percent duty cycle point of Ts is derived as follows: Ts/0.5 volt=100%/0.66 volt; Tx=(0.5/0.66)(100%)=76%. As illustrated in the waveform of FIG. 5D, Ts has shifted from the fifty percent duty starting point for 100 kHz frequency operation to seventy six percent duty starting point for 150 kHz frequency operation. The regulator loses slope compensation between fifty and seventy six percent duty cycle and thus becomes susceptible to sub-harmonic oscillation in that duty cycle range. If a higher frequency synchronization signal is applied to the oscillator, an even greater shift of Ts will occur. Moreover, as the slope of the compensation signal remains independent of operating frequency, Smax will attain only a small magnitude.
As VC is an indication of load, it can be monitored by internal circuitry, not shown, to detect light load conditions. In response to VC reaching a predetermined light load condition threshold, the operation can be changed to a “sleep mode,” in which some circuit elements can be deactivated to conserve power. At low duty cycles at which no compensation signal is produced, the level of VC corresponds to the amount of switch and regulator output currents. At higher duty cycles at which compensation signals are produced, the level of VC corresponds to a load level less than the actual load level. As the compensation signal increases with higher duty cycles, the load level correspondence decreases. For VC to be a reasonably accurate indicator of load level, the slope compensation Sx should be at the minimum signal magnitude necessary for compensation.
To obtain adequate compensation, a compensation signal of greater magnitude is required at increased duty cycles. The slope of the linear compensation curve thus is typically set to provide the appropriate magnitude for the maximum duty cycle operation. While this curve satisfies the maximum duty requirement, it over-compensates as duty cycle operation decreases to fifty percent. As the minimum necessary compensation between fifty percent and one hundred percent duty cycle operation is not linear, VC contains an unnecessary offset component through much of that range.
The need thus exists for a slope compensation arrangement that provides adequate slope compensation at fifty percent duty cycle and above for all operating frequencies. The need also exists to avoid over-compensation.